hpr-knowledge-base/hpr_transcripts/hpr3652.txt

Episode: 3652
Title: HPR3652: Registered memory
Source: https://hub.hackerpublicradio.org/ccdn.php?filename=/eps/hpr3652/hpr3652.mp3
Transcribed: 2025-10-25 02:53:16

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This is Hacker Public Radio Episode 3652 for Tuesday 2 August 2022.
Today's show is entitled Registered Memory.
It is hosted by JWP and is about 12 minutes long.
It carries a clean flag.
The summary is not to be confused with ECC memory, although memory modules often use both technologies.
Good day. My name is JWP and today I want to talk about registered memory.
Registered memory is buffered memory.
Sometimes you have unbuffered memory and maybe like in your home PC or something.
Registered memory is normally used on a server.
Registered memory again is also called buffered memory.
These memory modules have a register between the DRAM modules and the system's memory controller.
They place less electrical load on the memory controller and allow single systems to remain stable with more memory modules than they would have otherwise when compared with registered memory.
Conventional memory is usually referred to as unbuffered memory or unregistered memory.
When manufactured as a dual-inline memory module or DEM, a registered memory module is called an R-R-DEM.
While a unregistered memory module is called a U-DEM or simply DEM.
Registered memory is often more expensive because the lower number of units sold and additional security required.
It's usually found in only applications with a need for scalability and robustness outweighs the need for low price.
For example, registered memory is usually used in servers.
Although most registered memory modules also feature error-correcting code memory or ECC, it is also possible for the registered memory modules not to be error-correcting or vice versa unregistered ECC memory is supported and used in workstation or entry-level server boards that do not support a large amount of memory.
OK, so how's the performance of it?
Normally, there's a penalty for using registered memory.
Each reading write is buffered for one cycle between the memory bus and the DRAM.
So the register RAM can be thought of as running a clock cycle behind under a registered jam.
With SD RAM, this only applies to the first cycle of a burst.
However, the performance penalty is not universal and there may be other factors involved in memory access speed.
The Intel Westmear 5600 series access memory is interweaving wherein the memory access is distributed across three channels.
And if two dims are used per channel, the results and reduction of the maximum memory bandwidth for two DPC dims per channel configurations with you dim by some 5% in comparison with our DRAM.
This occurs because you go to two dims per memory channel due to the high electrical loading on the address control lines.
The memory controller uses a 2T or 2N timing for you dims and consequently every command that normally takes a single clock cycle is stretched to two cycles to allow for time setting.
So compatibility, usually the motherboard must match the memory type as a result, register memory will not work and a motherboard not designed for it and vice versa.
The same, some PC motherboards accept or require a registered memory but motherboards without ECC support or not even providing ECC functionality.
So compatibility issues arise when trying to use registered memory, it also supports ECC as described as ECC RAM and a PC motherboard does not support it.
So buffered memory types, and this is where it gets really, really, really confusing. So you have a registered or buffered dim which is our hyphen dim and modules and these modules insert a buffer between the pins of the command and address bus on the same dim and the memory chips.
A high capacity dim might have numerous memory chips, each of which must receive the memory address and their combined input capacity limits, the speed at which the memory bus can operate.
By redistributing the command and address the signals within the R dim, this allows more chips to connect to the memory bus.
The cost is increased memory latency as a result of one additional clock cycle required for the address to transfer the additional buffer.
Early registered RAM modules were physically incompatible with unregistered RAM modules but the two variants of SD RAM are dims are mechanically interchangeable and some motherboards may support both types and I can tell you from experience that that's very rare.
In the second type, this is a newer so it's called load reduced dims or LR dims and these modules are similar to R dims but add a buffer to the data lines as well.
In other words, LR dims buffer both control and data lines while keeping the parallel nature of all the signals as a result an LR dim provides a large overall maximum capacity while avoiding the performance and power consumption problems of FB dims introduced by the required conversion between serial and parallel forms.
So the next one is called a fully buffer dim or FB dim and this module increases the maximum capacities and large systems even more by using a more complex buffer chip to translate between wide bus of standard SD RAM chips and narrow high speed serial memory bus.
In other words, all control address and transfers to FB dims are performed in a serial fashion.
While additional logic present on each FB dim transfer transforms serial inputs into parallel signals required to drive memory chips by reducing the number of pins per memory bus.
CPUs could support more memory buses allowing a higher total memory bandwidth capacity.
Unfortunately the translation of further increased memory latency and the complex high speed buffer chips used significant power and generate a lot of heat.
Both FB dims and LR dims are designed primarily to minimize the low that the memory module presents to the bus.
They are not compatible with R dims and motherboards that require them usually do not accept any other kind of memory modules.
So there is something even newer and this is called DDR4 3DS dims and they in order to give DDR4 a mid-life kicker memory because DDR4 is a little old.
So there are many vendors that sell memory are opening their game and they are producing something called 3DS DDR4 dims.
So what is this 3DS? It is three-dimensional stacking of die in a single package.
Not to be confused with the twin die which is a two die next to each other and it is not stacked.
3DS uses TSV or through silicon VS to make the connection between the dies.
3DS is a game changer when it comes to dims of 128 gigabyte or 256 gigabyte and possibly 512 gigabyte on a single dim.
This is enabled by this technology. RD or LR dims can implement 3DS and have up to 4 ranks.
The 3DS protocol works by introducing the concept of logical ranks in addition to physical ranks.
So each part can be 2, 4 or 8 stacking.
The chip ID is C0, C0, 1 or C0, 0, 2 and decodes at 0, 8 logical ranks.
The second chip select gives 2 physical dims per dim.
An example of 2x physical rank and 4 logical rank dim.
It is happening now.
It is like if you really want to have the bigger ones.
If you are going to have 256 dims, you have to have an LR dim.
And you are not allowed to mix 3DS with non 3DS dims normally.
Okay, and this was pretty hard, pretty dry. I know it is an attack or public radio.
So take care and be safe. Have a good day.
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